BREQ
(redirected from Bus Request)

0.01 sec.

Acronym	Definition
BREQ	Bus Request
BREQ	Business Requirement

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? References in periodicals archive
It supports high-speed bus request and arbitration to minimize transfer latency. New PCI Bridge and Memory Controller Cores Take Connectivity to Board ... by Business Wire to offer complete flexibility in 66 MHz PCI bus request modes, the ability to interrupt memory writes on non-cache line boundaries and read on byte alignments as well as word alignments. DynaChip Introduces First Product to Support 66 MHz PCI; DY6000 ... by Business Wire chip directly controlled by the CUBIT is used to contain translation information); 2) bus request and access control, including backplane bus drivers; 3) bus reception with both backplane bus receivers and destination selection; and 4) output queuing, including cell prioritization based on the type of information being transported. TranSwitch starts general sampling of CUBIT; single chip implements ... by Business Wire More results

? References in periodicals archive

It supports high-speed bus request and arbitration to minimize transfer latency.

New PCI Bridge and Memory Controller Cores Take Connectivity to Board ... by Business Wire

to offer complete flexibility in 66 MHz PCI bus request modes, the ability to interrupt memory writes on non-cache line boundaries and read on byte alignments as well as word alignments.

DynaChip Introduces First Product to Support 66 MHz PCI; DY6000 ... by Business Wire

chip directly controlled by the CUBIT is used to contain translation information); 2) bus request and access control, including backplane bus drivers; 3) bus reception with both backplane bus receivers and destination selection; and 4) output queuing, including cell prioritization based on the type of information being transported.

TranSwitch starts general sampling of CUBIT; single chip implements ... by Business Wire

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BURSI
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BREQ (redirected from Bus Request)

BREQ
(redirected from Bus Request)