a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that the company will present their design and verification software for SoC design, which features NAND Flash and DDR-DRAM
solutions used in a wide range of mobile, multimedia, and consumer electronics, in their stand (M51) at the DATE (Design Automation and Test Europe) conference held on April 17-19, 2007 in Nice, France.
The specification is the result of a collaborative effort by industry leaders, ARM, Denali, Rambus, Intel, Samsung and Synopsys to describe a common interface between DDR-DRAM
memory controller logic designs and DDR DRAM physical interface (DDR PHY) designs.
Designers are increasingly challenged with overcoming memory bandwidth bottlenecks to ensure that various on-chip processing units, such as cpu, dsp, and video processors have efficient access to data from off-chip DDR-DRAM
ARM, Denali, Intel, Rambus, Samsung, and Synopsys team on specification to address development challenges for DDR-DRAM memory systems
The specification is the result of a collaborative effort by industry leaders to describe a common interface between DDR-DRAM memory controller logic designs and DDR DRAM physical interface (DDR PHY) designs.
TI customers benefit by gaining access to Denali's latest generation of Databahn(TM) memory controller IP, a key design block, which optimizes the interface between complex IC chips and DDR-DRAM
Suite of IP Products Target DDR-DRAM
, PCI Express, Serial ATA, CE-ATA, USB, and Other Standard Interfaces