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Additionally, the new SerDes core features Avago's proprietary clockless Decision Feedback Equalization, on-chip BERT for channel bit error rate optimization, LC-based oscillator for improved power-supply noise rejection, and 1149. Utilizing an innovative adaptive decision feedback equalization ( Using PAM4 multilevel signaling up to 10 gigabits per second (Gb/s), and Decision Feedback Equalization (DFE) up to 5Gb/s, the Accelerant technology provides a highly efficient, low power option for designers of system, storage and network infrastructure equipment to upgrade existing backplanes and cables to higher data rates as well to insure that new system designs will support longer product life-spans. |
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