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DIB
(redirected from Dual Independent Bus)

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AcronymDefinition
DIBDubai Islamic Bank
DIBDevice Independent Bitmap
DIBDirectory Information Base
DIBDisability Insurance Benefits
DIBDual Independent Bus (Architecture)
DIBDiffuse Interstellar Bands
DIBDeutsche Internetbibliothek (German Internet Library)
DIBDefense Industrial Base
DIBDCGS Integration Backbone
DIBDiagnostic Interview for Borderlines (Psychology)
DIBDiameter Inside Bark (logging)
DIBDevice Interface Board
DIBDifficulty in Breathing
DIBDead in Bed
DIBDibrugarh, India - Chabua (Airport Code)
DIBDiisobutylene
DIBDefense Information Base
DIBDrenched in Blood (Turbonegro song)
DIBData Input Bus
DIBData Information Base
DIBDirect I/O Bridge
DIBDetector Interface Board
DIBDanish International Brigade
DIBDrop in Box
DIBDoin' it Big
DIBDay in Bed
DIBDaily Information Bulletin
DIBData Interface Buffer
DIBDevice Interface Bus
DIBDefense Intelligence Board
DIBDipartimento di Informatica dell'università di Bari (Bari, Italy)
DIBDisabilities Issues Board
DIBDigital Information Bank Company
DIBDavidson International Baccalaureate (Davidson, NC)
DIBDoor Impact Beam
DIBDefense Intelligence Bureau (China and Taiwan)
DIBDesk Instruction Booklet
DIBDaily Intelligence Bulletin
DIBDistributed Integrated Backbone (US DoD)


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The processor integrates the P6 Dynamic Execution micro-architecture, Dual Independent Bus (DBI), a multi-transaction system bus and the Intel(R)MMX(TM) media enhancement technology.
Product Features, Price and Availability The Pentium II processors at 350 and 400 MHz include all of the same performance-enhancing features as the current Pentium II processors, including: Dual Independent Bus architecture, Dynamic Execution, Intel MMX technology and a closely coupled 512 KB Level 2 (L2) cache bus running at half the speed of the processor (for the 400-MHz processor, the L2 cache bus runs at 200 MHz).
25 micron process technology and offer the same performance-enhancing features as the existing Pentium II processors for the desktop segment, including: Dual Independent Bus architecture, Dynamic Execution, Intel MMX(tm) technology and a closely coupled 512KB Level 2 cache.
 
 
 
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