EJTAG

AcronymDefinition
EJTAGEnhanced JTAG (MIPS processors)
References in periodicals archive ?
FS2 System Navigator tools provide best-in-class performance analysis and debug capabilities for 74K-based designs by giving customers full access to the debug features of MIPS([R]) EJTAG, and allowing them to leverage the advanced out-of-order instruction processing, enhanced DSP capabilities and CorExtend[TM] user-defined instructions in the 74K cores.
It connects to the target system using the standard EJTAG 14-pin connector.
Core-centric debug features like EJTAG and PDtrace are just part of the FS2 portfolio of system-level debug solutions.
It connects to the target system using the standard EJTAG 14-pin connector for on-chip trace or a 38-pin Mictor connector for off-chip trace capture.
It connects to the MIPS target using the standard EJTAG 14-pin connector for on-chip trace or a 38-pin Mictor connector for off-chip trace capture.
This was achieved by working with MIPS Technologies to develop windows specific to the MIPS EJTAG debug and PDTrace tracing features.
Enabling GDB to support EJTAG hardware assisted debugging with additions like complex triggers and real-time trace windows provides a seamless toolchain for GNU users.
EPI's EDB source level debugger and MAJIC(R) intelligent EJTAG debug probe, combined with a broad complement of debugger APIs, provides the industry's most comprehensive support for all phases of system development.
In addition to supporting the newer IDT RC32438 device, the EPI EJTAG tools support all the devices within the IDT Interprise(TM) processor family, including the RC32355 and RC32351 processors targeting CPE applications, and the RC32332, RC32333 and RC32334 processors targeting gateway and Ethernet switching applications.
These integrated peripherals include one 10/100 Ethernet MAC, USB Host and Device controller, PCMCIA/Compact Flash interface, IrDA controller, AC97 interface (external CODEC required), two Secure Digital (SD) controllers, three UART's, two SSI controllers, EJTAG, and 48 General Purpose I/O (GPIO) pins.
In addition to the run control and debugging features that are accessible through the MIPS EJTAG port, the device features the FS2 CLAM(R) (Configurable Logic Analyzer Module) which allows the user to trace and trigger on up-to 128 specified internal nodes (32 at a time) within the programmable logic fabric.
Debugging is easily accomplished using the on-board EJTAG bus and associated CLAM debugging tools.