In order to deliver necessary data for the users' research activities quickly and with high reliability, JAIST replaced two previous systems with Dell Compellent, providing a combination of both high performance and high capacity to manage a large volume of data in one solution.
When updating its centralized storage system, JAIST faced a number of challenges, including achieving fast data access and constructing efficient back-up for large data sets.
With Dell Compellent's automated data tiering technology, JAIST can benefit from both the performance and capacity from a single system, which previously had been managed separately.
At JAIST, it is imperative to provide our world-class scientists with the best available technology resources to support their computational research," said Professor Mineo Kaneko, director of the JAIST Research Center for Advanced Computing Infrastructure at JAIST.
The Cray-Altair partnership ensures that top global research organizations like JAIST have the reliable, efficient and well-supported supercomputing resources needed for their groundbreaking scientific work.
The increasing complexity of challenges that organizations such as JAIST are working to solve is the reason why we remain committed to developing and providing solutions that serve both industry and education," said Ryutaro Ishimoto, president of SGI Japan.
The JAIST system parallel computer with a cache-coherent shared memory architecture comprises of 96 processor memory blades, each configured with two Intel[R] Xeon[R] E7 series processors (16-cores) and 128GB of memory, using a NUMAlink[R] 5 (15GB/second) interconnect.
Digital watermark detection by software alone is too slow and power hungry, and it cannot catch illegal audio files that are exchanged over the Internet," said Yasushi Inoguchi, associate professor at the center for information science at JAIST.
Supported by Celoxica and Japan's Science and Technology Agency (JST), JAIST researchers used Celoxica's DK Design Suite to design the watermarking algorithms and implement them from C to hardware.