JTAG


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AcronymDefinition
JTAGJoint Test Action Group (developer of IEEE Standard 1149.1-1990)
JTAGJoint Test Advisory Group (US DoD)
JTAGJoint Technical Assessment Group
JTAGJoint Technical Advisory Group
JTAGJoint Technical Activities Group
References in periodicals archive ?
Because DDR3 memory chips have become so prevalent in high-speed systems, I used this technology as the basis for explaining how JTAG or boundary-scan methods can be integrated into every step of a system's lifecycle, beginning in design and transitioning into manufacturing and field service.
JTAG is a physical method of accessing data on smart phones and mobile devices that can be especially useful for locked devices, or when forensic software does not work.
The UART and Manchester encoding modes support the Serial Wire Viewer (SWV) and the embedded Trace Buffer (ETB) and JTAG adaptive clocking are supported and all JTAG signals can be monitored.
Out of this context the JTAG group began forming a boundary scan test strategy.
Symphony/TS/CFM incorporates JTAG Technologies' boundary scan controller and TAP Interface Modules inside Teradyne's test system (using Teradyne's flexible Custom Function Board).
All TI JTAG emulators, including the new XDS200, can be controlled through a software integrated development environment (IDE), such as TI's Code Composer Studio (TM) IDE, which can be utilized across TI's entire embedded processing portfolio.
The tool allows designers to easily incorporate their FPGA hardware directly into The MathWork's Simulink(R) tool using a JTAG interface.
Until now, when development teams needed to get JTAG visibility at the protocol layer, they had to take physical-level measurements and manually decode the JTAG signals, a time-consuming and error-prone process.
Many of our customers are already clients of both Corelis and Corelis' sister company, Blackhawk, a leading provider of JTAG emulators for our entire line of DSP products.
The XJTAG XTR series supports multiple JTAG chains - with up to four Test Access Port (TAP) connections available to a target board.
Using the XDS510USB PLUS JTAG emulator and the DiaTem Debugger, the designer can now test the most critical portions of their target board that are connected via boundary scan logic.