LVPECL

AcronymDefinition
LVPECLLow Voltage Positive Emitter Coupled Logic
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GRL testing of the LVPECL DSC1122 found that it surpassed 6G SAS compliance requirements with 59% lower transmitter jitter than the SAS 2.
The LVPECL and LVDS oscillators feature application specific integrated circuits (ASICs) for accurate performance, decreased cost and increased flexibility.
This feature allows the device to accept LVPECL, CML and LVDS logic level standards.
The NBXzzzzzz series of single- and dual-frequency modules provide ultra low jitter and ultra low phase noise LVDS and LVPECL differential outputs respectively.
Pricing for XpressO LVPECL and LVDS versions will vary depending on the output, frequency and stability needed.
0-210 MHz LVCMOS single ended clock source and generates a differential LVPECL output and a single ended LVCMOS output at a selectable clock output frequency which is a multiple of the input clock frequency.
The devices offer a wide output frequency range from25 MHz to 3000 MHz and LVDS and LVPECL outputs with adjustable amplitudes.
The ability to independently configure each output as LVCMOS, LVDS or LVPECL at any frequency makes this an ideal solution for switches/routers, AV timing and FPGA clocking.
The LVDS / LVPECL oscillators feature less than one picosecond of jitter and can be rapidly configured to the desired output frequency without the need for tuning.