LVTTLLow Voltage Transistor Transistor Logic (AMCC)
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The I/O pins support LVTTL and LVDS transmit signaling and can be factory-configured for LVDS receive operation.
The card features two successive approximation register (SAR) 16-bit A/D channels, two SAR 16- bit D/A channels, 16 bits of LVTTL input, and 16 bits of digital LVTTL output all synchronously-sampled under the control of a precision, user programmable instruction sequencer implemented within the onboard FPGA.
The device accepts differential LVPECL, CML, or LVDS levels as well as single-ended LVPECL, CML, LVCMOS or LVTTL with the proper VREFAC supply.
An LVPECL trigger input, an LVPECL output, an LVTTL output and the sample clock input are provided on the front panel.
3V: crystal, LVTTL, LVCMOS Availability and Pricing:
Another enhancement is the implementation of rolled edge rates of the LVTTL outputs to further reduce EMI.
The DS90C3202 receiver receives the LVDS data and converts it back to the original 70-bit LVTTL (low voltage transistor-transistor logic) stream for use by panel control ASICs and timing controllers.
Both the transmitter and receiver devices contain LVTTL video ports (60-bit wide) and digital audio ports (SPDIF and I2S) for direct interface with commercially available audio-video processors.
The I/O ports support several standards, including LVTTL, PCI(TM), PCI-X(TM), GTL+, LVCMOS2.
In addition, both devices utilize the ON Semiconductor's AnyLevel(TM) input structure, which provides seamless interfacing with LVPECL, CML, LVCMOS, LVTTL, or LVDS signals and offers true design flexibility.
These mixed-output low-voltage PECL and low-voltage transistor-to-transistor (LVTTL) devices provide timing module and voltage-controlled crystal oscillator designers integrated low-voltage PECL and LVTTL outputs in a 3 x 3 mm and 4 x 4 mm package, respectively.