NFET

AcronymDefinition
NFETNewquay for Excellence Training (Cornwall, England, UK)
nFETNegative Channel Field Effect Transistor
NFETNuclear Field Electronics Technician (US Navy rating)
References in periodicals archive ?
With this mixed strain approach, the nFET uniaxial strain can be amplified by the substrate, while the pFET can be enhanced beyond levels offered by conventional uniaxially strained silicon.
The SP6132 has a highly efficient 300KHz PWM architecture that drives dual NFET switches with efficiencies as high as 95%.
The VPNP can be paired with either a SiGe NPN, for a complementary SiGe BiCMOS process, or with an NFET device to achieve high-current complementary push-pull functions needed in circuit designs that require balanced performance, such as disk drive pre-amplifiers or laser drivers.
Among the unique features included in CMOS 6RF technology are a dual oxide option with compliance for handheld device voltage levels, a low conductivity substrate, a triple-well NFET for improved isolation and a suite of high quality passive elements from IBM's SiGe bipolar process, such as a thick last metal option for inductors, MIM and MOS capacitors, varactors and precision resistors.
Sipex's proprietary AnyFET(TM) technology allows the SP6120 to be used as a tool for resolving a multitude of price/performance trade-offs by allowing the user to select the high side- switching device, NFET or PFET, without having to change controllers.
The CS-51311 is a synchronous dual-NFET buck regulator that drives a pair of external power NFETs which in turn supply current and voltage to the motherboard's core logic.
The CS-51312, a synchronous dual-NFET buck regulator, drives a pair of external power NFETs which in turn supply current and voltage to the core logic.
NFETs actively control inrush current to prevent FET damage
Included on the chip is sequencing, drive circuitry for high voltage external NFETs, voltage monitoring and protection.
Addressing The Gate Stack Challenge For High Mobility InxGaAs Channels For NFETs - This collaborative work (between Intel, SEMATECH, University of Texas Austin, SUNY Albany, Stanford, and University of Oklohoma), addresses key gate stack issues including a) EOT scalability for high performance and electrostatic control with acceptable leakage at operating and off-state, b) understanding the impact of charge trapping, c) thermal stability on InGaAs, and d) the impact of In% on interface on surface channel MOSFETs.