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SiByte processors are designed for maximum I/O throughput, with three 10/100/1000 Ethernet MACs, a 32-bit/66MHz PCI host bridge, HyperTransport Host Bridge, SMBus, GPIO, flash interface, interrupts, and DMA all integrated onto the single chip. New PCI host bridge and memory controller interface intellectual property (IP) cores are now available for the ARCtangent(TM)-A4 processor, a leading user-customizable 32-bit processor. The PowerPC Suite of cores is scheduled to be introduced later this year, including a PCI host bridge, PowerPC bus master, PowerPC bus slave, and PowerPC bus arbiter. |
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