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PMOS |
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By optimizing shallow trench isolation (STI) stress, sidewall stress, and silicon nitride (SiN) stress on the gate, it was possible to improve the performance of both NMOS and PMOS. Available in volume production today, the PIC16F630 and PIC16F676 devices feature Microchip's PMOS Electrically Erasable Cell (PEEC) process technology, which provides best-in-class erase/write endurance, retention, and disturb reliability for both program and on-chip data EEPROM memory. These devices also provide a wide (20V max) operating voltage, while their PMOS pull-up and NMOS pull-down transistors provide a 17V signal swing (VCC - VEE). |
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