QSPI

AcronymDefinition
QSPIQueued Serial Peripheral Interface
References in periodicals archive ?
Very low RBOM requiring only a single crystal, QSPI flash, and antenna with a single input power rail.
technology, along with secure boot, hardware cryptography, RSA/ECC, on-the-fly encryption/decryption on DDR and QSPI memories, tamper resistance, memory scrambling, independent watchdog, temperature, voltage and frequency monitoring and a unique ID in each device.
SPI, QSPI and a Microwire-compatible interface enable high-speed data access to the AS1528/29 while minimising board space.
SPI, QSPI and Microwire are trademarks of National Semiconductor.
SPI, QSPI and a Microwire-compatible interface enable high-speed data access while minimizing board space, while an integrated 2.
0B controller -- 3 UARTs -- QSPI -- Inter-IC (IIC) bus interface -- 4 ch.
Standard ColdFire peripheral set (UARTs, QSPI, timers and I2C)
1) MIPS at 166MHz -- eMAC module and hardware divide -- Eight KB I/D-cache,16KB SRAM -- Optional 10/100 Ethernet media access controller -- Three UARTs -- QSPI -- Inter-IC bus interface -- Four 32-bit timers with DMA support -- 16-channel DMA controller -- 16-bit DDR / 32-bit SDR SDRAM controller -- Up to 50 general-purpose I/O -- System integration: phased-lock loop (PLL), software watchdog -- 1.