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QSPI |
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1 MIPS @ 80 MHz -- Multiply-Accumulate (MAC) module and Hardware divide -- Up to 32K bytes SRAM -- Up to 256K bytes flash with 100K write/erase cycles and 10 years data retention -- 3 UARTs -- Queued serial peripheral interface (QSPI) -- Inter-IC (IIC) bus interface -- 4 ch. nbsp;interface and queued serial peripheral interface ( with two asynchronous serial communications interfaces (SCI) -- Queued Serial Module (QSM) that integrates a queued serial peripheral interface (QSPI) with a 16-entry transfer queue -- Enhanced single-chip integration module (SCIM2) that combines address and data pins usable as I/O ports with nine on-chip programmable chip selects, watchdog timers, periodic timer, and PLL clock generator -- 16. |
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