The device provides OC-48 performance that seamlessly interfaces to ASICs and network processors through the industry standard SSRAM
port 1200 uses an advanced programmable classification engine to non-intrusively monitor packet data on an SSRAM
interface or the high-speed IX data bus on the Intel(R) IXP1200 network processor.
The CYNCP80192 offers an SSRAM
interface, offloads table and pipeline management from the processor, and offers a silicon-optimized ASSP solution to customers.
Additionally, the iAP uses a ZBT/DCD SSRAM
interface, making it simple to incorporate the iAP into a wide variety of NPU or ASIC-based designs, including those based on the complete iFlow Data Path Processing Platform (DP3) chipset.
The LNI8010 provides an SSRAM
interface on the system bus that enables easy interfacing to popular network processors as well as to system ASICs.
The controller provides a 64-bit wide port that operates at a full 125Mhz data rate, and supports SSRAM
, SDRAM, and Flash EEPROM with up to a 1GByte-per-second transfer rate.
port 1100 examines packet data on an SSRAM
interface or equivalent, as it is written into a memory or FIFO queue.
The controller supports DDRAM, SDRAM, DRAM, Flash, SSRAM
and ROM devices, as well as multiple backside host interfaces and memory banks.
600 MHz Alpha 264 CPU and 2MB SSRAM
cache in Alpha Slot B module