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Starting with the silicon wafer material itself, the book covers various aspects of the device from advanced gate dielectrics through source/drain engineering, and ends with a summary on fully silicided gates. As scaling continues, one of the most pressing concerns of CMOS technology beyond the 45 nm node is the contact resistance in source/drain regions, which comes from a relatively high Schottky barrier between n-type doped Si and nickel Advanced gate stack, source/drain and channel engineering for si-based CMOS 3; new materials, processes and equipment; proceedings. |
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