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The MIPS32 4KE family currently includes the 4KEp(TM) core, which consists of the base configuration; the 4KEm(TM), which features a fast multiplier; and the 4KEc(TM), which features a fast multiplier as well as a memory management unit with a translation lookaside buffer (TLB). It uses a 4-Kbyte-page size, 16-, 32- or 64-entry joint translation lookaside buffer (TLB). The MMU's 48-double entry translation lookaside buffer (TLB) with its fourway set-associative 32-KByte instruction and data caches allows the core to meet Windows CE(TM) MMU requirements. |
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