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3 XAUI through the appropriate PHY and transformer logic to IEEE 802.
The DesignWare PHY IP for PCIe, XAUI, and SATA, combined with the respective DesignWare digital controllers and verification IP, delivers a complete set of IP solutions for these protocols.
Synopsys is porting DesignWare PHYs for the popular PCIe, SATA and XAUI protocols to the 65-nm process node to give designer's access to standards-compliant IP with high-value features, such as low power and small area.
In addition, Xilinx' participation in three XAUI group tests has resulted in an extensive portfolio of XAUI devices with which the Virtex-II Pro FPGA using the XAUI IP core can interoperate.
There are three active multi-vendor agreements for transponders supporting the XAUI interface--XENPAK, XPAK and X2.
The QuadPHY 10GX is a bi-directional XGMII to XAUI (10 Gigabit Attachment Unit Interface) transceiver with a fully redundant XAUI interface for working and protect switching architectures.
The S/UNI 1x10GE-XP solution addresses the market adoption of XAUI as a PHY-to-module interface for 10GE optics.
In a test at the University of New Hampshire InterOperability Laboratory in July, Mindspeed, Tyco, Blaze, and other vendors proved that their XAUI devices designed to the IEEE 802.
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