XGMII

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Acronym	Definition
XGMII	10 Gbit Media Independent Interface

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? References in periodicals archive
Included with the XAUI core are the XGMII Extender Sublayers (DTE and PHY XGXS) and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802. Xilinx provides proven XAUI solution for 10 Gigabit Ethernet ... by EDP Weekly's IT Monitor TaraCom has ported the Serial ATA (SATA) core intellectual core property (IP) for integration into SoC and ASIC designs ranging from XAUI compliant, PCS/PMD functionality of the 10 Gigabit Ethernet XAUI and 10 Gigabit Fibre Channel specs as well as SATA, PCI Express, XGMII and other related applications. SerDes/PHY IPs in 90 and 65-Nanometer by Business Wire The QuadPHY 10GX is a bi-directional XGMII to XAUI (10 Gigabit Attachment Unit Interface) transceiver with a fully redundant XAUI interface for working and protect switching architectures. PMC-Sierra announces 10 Gigabit Ethernet and 10 Gigabit Fibre Channel ... by EDP Weekly's IT Monitor More results

? References in periodicals archive

Included with the XAUI core are the XGMII Extender Sublayers (DTE and PHY XGXS) and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802.

Xilinx provides proven XAUI solution for 10 Gigabit Ethernet ... by EDP Weekly's IT Monitor

TaraCom has ported the Serial ATA (SATA) core intellectual core property (IP) for integration into SoC and ASIC designs ranging from XAUI compliant, PCS/PMD functionality of the 10 Gigabit Ethernet XAUI and 10 Gigabit Fibre Channel specs as well as SATA, PCI Express, XGMII and other related applications.

SerDes/PHY IPs in 90 and 65-Nanometer by Business Wire

The QuadPHY 10GX is a bi-directional XGMII to XAUI (10 Gigabit Attachment Unit Interface) transceiver with a fully redundant XAUI interface for working and protect switching architectures.

PMC-Sierra announces 10 Gigabit Ethernet and 10 Gigabit Fibre Channel ... by EDP Weekly's IT Monitor

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