To minimize the costs of using CLIPPER in a product, CLIPPER is available as a small module containing the processor, two cache and
memory management units, and the clock; thus the user doesn't have to build his own cache or memory management system.
Other features include a
memory management unit suitable for multi-application cards and support for operating voltages from 1.6V to 5.5V.
The enhancements include an expanded
memory management unit that is now capable of managing pages from 1KB to 256MB, improved control of caches and increased co-processor support.
The first chip to result from the alliance, the L7200, includes an ARM 720T processor core with 8Kbyte cache, write buffer and
memory management unit, along with several integrated AMBA (Advanced Microcontroller Bus Architecture) peripherals.
The ARM926EJ-S macrocell is fully synthesizable and features a 32-bit RISC CPU, enhanced DSP functionality, ARM Jazelle(R) technology, flexible size instruction and data caches, tightly coupled memory (TCM) interfaces and a
memory management unit (MMU) that supports leading operating systems such as the Symbian OS, Linux, and Windows CE.
The ARM926EJ-S soft macrocell is a fully synthesizable, high-performance 32-bit RISC processor comprising the Jazelle technology-enhanced processor core, instruction and data caches, tightly coupled memory (TCM) interfaces,
memory management unit (MMU), and separate instruction and data AMBA bus-based AHB (Advanced High-performance Bus) interfaces.
Features of the 4Kc hard core include 16K instruction and data caches, a TLB
memory management unit and a die size of less than 7sq/mm when using TSMC's 0.18-micron process.
The on-chip
Memory Management Unit (MMU) incorporates hardware firewalls to isolate and protect applet code from other system elements.