L.Cadix, et al, "Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs
," Interconnect Technology Conference (IITC), 2010 International.
Lee, "Architectural evaluation of 3D stacked RRAM caches," in Proceedings of the IEEE International Conference on 3D System Integration (3DIC
'09), September 2009.
Thus several new DRAM memory architectures based on 3D layer stacking and TSV have evolved to carry memory technology forward, explains research group Yole Developpement in its recently released report on 3D ICs titled "3DIC
& 2.5D TSV Interconnect for Advanced Packaging--2014 Business Update."
It is styled as a 'Bridge Technology to 3DIC
' to provide a solution using established wire-bond assembly techniques to enable low power and high-bandwidth (1000 IO+) packaging in an ultra-small form factor.