ADPLLAll-Digital Phase-Locked Loop
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In past years, we have created a lot of scripting for design, verification, and lab analysis of the ADPLL such that we are able to transfer a significant verification package to our customers.
"We are proud that we have developed the low-power ADPLL with imec," commented Isao Matsumoto, director, LSI Production Headquarters/LSI Product Development Headquarters at ROHM, in a press release.
Form (6), we can see that to obtain the based-model discrete-time transfer function of the ADPLL, the values of the parameters, [C.sub.1], [C.sub.2], [k.sub.d], and [k.sub.o] are needed.
On the other hand, taking (4) into (3), and the z-domain transfer function of the ADPLL based on bilinear transformation can be obtained:
Let us set the denominator of the two z-domain transfer functions of the ADPLL; (6) and (7) obtained by different methods to be equal and the two equations about [C.sub.1] and [C.sub.2] can be given:
Namely, assuming that the PD of ADPLL lies in its linear operation range and for ADPLL the characteristic of frequency response is within the range of its passband.
In the following, we are going to discuss the range of [w.sub.n] from the two aspects, fast capture bandwidth of ADPLL, and its loop SNR, so as to make a compromise between the locked-in range and the tracking precision.
In the case of ADPLL, there are two kinds of noises, external phase noise and internal phase noise.
The channel of deep-space communication is quite benign, with AWGN being the dominating impairment [1], and thus the phase noise of ADPLL caused by AWGN can be given by [13]
where [B.sub.i] is the bandwidth of input signal of the ADPLL, [(S/N).sub.i] is its input SNR, and [B.sub.L] is loop noise bandwidth.
For the second-order ADPLL taking proportion integral filter as its loop filter, BL can be expressed as
For ADPLL, the ability to suppress noise can be reflected by the loop SNR: