ASITICAnalysis and Simulation of Inductors and Transformers for Integrated Circuits (multi-layer silicon substrate analysis tool)
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More precisely, the obtained values are within +6 percent (ASITIC) and the -6 percent (FDTD).
Again, it is apparent that the agreement obtained with the FDTD simulation is better than that achieved with ASITIC. This follows from a better modeling of the peak input resistance attainable with the numerical approach.
The results have been compared with both ASITIC simulations and experimental measurements, The latter are available only for the structures implemented in this chip, namely the two-turn inductor described above and a 0.25 turn inductor (a direct connection between input mad output ports).