(redirected from Back-End-of-Line)
BEOLBack-End-of-Line (electronics)
BEOLBent's Old Fort National Historic Site (La Junta, Colorado)
BEOLBent's Old Fort National Historic Site (US National Park Service)
References in periodicals archive ?
The IC uses TowerJazz's 130nm copper back-end-of-line technology, customised to meet specific optical performance.
At Imec, we tackle the full process flow, including designing readout pixels and circuitry, and develop back-end-of-line interconnects that are processed on readout wafers in Imec's 200mm fab.
Abstract: The objective of this study was to assess and improve reliability of back-end-of-line (BEoL) region comprising of Cu/low-k interconnect layers and Far-BEoL (fBEoL) region consisting of flip chip (C4) [mu]-bumps during the process of die attachment to substrate.
Intrinsic reliability test applications are often segregated between back-end-of-line (BEOL) and front-end-of-line (FEOL).
The company said the Supremas will be used in front-end-of-line (FEOL), mid-of-line (MoL) and back-end-of-line (BEOL) strip applications for high-volume production at the 3Xnm technology nodes and advanced device development at the 2Xnm nodes.The systems have begun shipment in Q3 2010.
Novellus' GxT system provides advanced photoresist strip technology for the most demanding applications, including low silicon loss, high dose implant strip, plasma assisted doping, and reducing chemistries required for back-end-of-line clean applications.
Papers from a September 2006 conference, 86 in all, cover all aspects of the use of ultra-clean technology for large-scale integration of semiconductors, and cleaning and contamination-control in both front- end-of-line (FEOL) and back-end-of-line (BEOL) processing.
"Mattson's sustained strip leadership in the foundry market is proof that our systems continue to deliver the processing and productivity performance our customers value for both front-end-of-line and back-end-of-line applications," said Stephen T.
In these proceedings from the September 2004 symposium, contributors describe their research in ten major topic areas, including surface preparation for gate dielectric with high dielectric constants, front-end-of-line and back-end-of-line cleaning, rinsing and drying, wet and gaseous etching, challenges and cleaning methods for particles and alternative cleaning methods, metrology, contamination control, post-CMP cleaning, and wet photo resist removal.