BLR

(redirected from Board Level Reliability)
AcronymDefinition
BLRBelarus
BLRBusiness & Legal Reports
BLRBureau of Labor Relations (Philippines)
BLRBoucle Locale Radio (French: Wireless Local Loop)
BLRBoiler
BLRBureau of Land Records (Pennsylvania)
BLRBinary Logistic Regression
BLRBroad-Line Region
BLRBottom Line Records (San Diego, CA)
BLRBase Lending Rate
BLRBourg-la-Reine (French: Town of the Queen; French village)
BLRBinary Language Representation
BLRBig Lazy Robot (visual effects studio; Spain)
BLRBoard Level Reliability (packaging)
BLRBintan Lagoon Resort (Indonesia)
BLRBangalore, India - Hindustan (Airport Code)
BLRBeyond Local Repair
BLRBrowning Lever Rifle (Lever Action Browning Rifles)
BLRBank Loan Rating
BLRBureau of Legislative Research (Arkansas Legislative Council; Little Rock, AR)
BLRBulharská Lidová Republika (Czech: People's Republic of Bulgaria)
BLRBusiness and Legal Resources (Old Saybrook, CT; compliance consultancy)
BLRBlack Labrador Retriever
BLRBoundary Location Register
BLRBalanced Likelihood Ratio
BLRBattery Level Radar (vehicle-mounted radar)
BLRBlock Level Retransmission
BLRBlock Length Register
BLRBlue-Light Radiation
BLRBaseline Requirements Document
BLRBelow Layer Range
BLRBoîte Aux Lettres Rurale (Canada Post)
References in periodicals archive ?
Amkor has shown through simulations and actual test data generated by customers that fillets--if formed--can improve board level reliability as much as two times for a package with large die-to-package size ratio.
Lee, "A Comprehensive Parallel Study on the Board Level Reliability of SAC, SACX, and SCN Solders," Electronic Components and Technology Conference, May 2008.
This includes 2x the board level reliability of a standard FC PBGA or FC ceramic BGA, as well as full signal wiring on both sides of the core, according to the company.
Soldering EIAJ RCX-102/102 N=5, OK heat Resistance EIAJ RCX-102/103 N=5, OK to dissolution BOARD LEVEL RELIABILITY TESTING Condition Results MIL-STD-883E, Temperature cycling Method 1010.
L," Experimental studies of board level reliability of chip-scale package subjected to JEDEC drop test condition" Journal of Microelectronics reliability No.