One of the fundamental parameters that can be derived from C-V accumulation measurements is the silicon dioxide thickness.
Figure 3 is the block diagram of a basic C-V measurement setup.
Although a block diagram of a C-V test setup looks deceptively simple, certain challenges are associated with this testing.
* C-V instrument connections through a prober to the wafer device
In most test environments, the DUT is a test structure on a wafer: It is connected to the C-V instrument through a prober, a probe card adapter, and a switch matrix.
Because of the complexity of the hardware, cabling, and compensation techniques, it is a good idea to confer with C-V test application engineers.
In addition to accuracy issues, practical considerations in C-V data collection include the instrumentation's range of test variables, versatility of parameter extraction software, and ease of hardware usage.
Some researchers also may be interested in less common tests such as performing both a C-V and C-f sweep on a metal-insulator-metal capacitor, measuring small interconnect capacitance on a wafer, or doing a C-V sweep on a two-terminal nanowire device.
Often, engineers and researchers are expected to perform C-V measurements with little experience and training on the instrumentation.