The effect of the differential pair mismatch of the CCCII in Fig.
The parasitic resistance of the proposed CCCII with [R.
In the literature, electronically tunable intrinsic resistance was used to advantage in CCCII , .
The simulated frequency response of the current gain from port X to port Z for the CCCII has been plotted in Fig.
5 depicts the changing simulated percent total harmonic distortion (THD) plot versus peak to peak input current for the CCCII.
x2] are the intrinsic resistances of the CCCII with [R.
CCCIIs with negative resistance realizations were introduced in , .
As an application, the proposed BiCMOS CCCIIs are used to build an electronically tunable grounded inductance simulator as shown in Fig.