References in periodicals archive ?
Chaudhury, "Comparative study of leakage power in CNTFET over MOSFET device," Journal of Semiconductors, vol.
Kim, "Modelling a CNTFET with undeposited CNT defects," in Proceedings of IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, Kyoto, Japan, October 2010.
Lombardi, "A novel design methodology to optimize the speed and power of the CNTFET circuits," in Circuits and Systems, 2009.
In the reminder of paper is organized as follow: In section 2 presents a review of CNTFETs. Previous works are described in section 3.
Due to the inaccurate chip fabrication of CNTFET technology, diversity of using CNTs with different diameters decreases the manufacturability issue.
All circuits are simulated with Synopsys HSPICE and 32 nm CNTFET technology [27, 28] in three power supply voltages (1V, 0.9 V, and 0.8 V) at room temperature.
A carbon nanotube field effect transistor (CNTFET) is modeled as: two metal contacts are deposited on the carbon nanotube quantum dot to serve as source and drain electrodes.
To consider the possibility of using CNTFET for SRAM, in [6, 7] the authors have compared CNTFET and MOSFET SRAM cell.
Section 3 considers the design of CNTFET based SRAM cell design for various topologies.
Therefore, it is essential to utilize interconnects as short as possible to tap the high-frequency capability of the CNTFETs  and GNRFETs.
The layout of a CNTFET device is depicted in Figure 1.
The typical width of a high-tech CNTFET device is reported  to be 1 [micro]m.
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