Another way of performing down conversion without the sine or cosine look-up tables is the CORDIC (Co-Ordinate Rotation Digital Computer) algorithm.
In the circular rotation mode the CORDIC computes the Cartesian co-ordinates of the target vector [v.
After n iterations the CORDIC equations result in [x.
The accuracy is determined by number of iterations and the word length of the CORDIC processor.
After n=1 iterations the CORDIC provides the sample I(k) and Q(k) of the down converted Inphase and Quadrature phase signal with a resolution of approximately n bits.
The CORDIC can be implemented using pipelined architecture.
In this section simulation results are presented to compare the performance of the CORDIC & ROM LUT based algorithms for the design of DDC.
Graphs 1,2,3,4 shows the plot of BER, AvBER vs number of iterations for both CORDIC and ROM- LUT methods.
The results shows that for CORDIC DDC BER remains a constant value of 0.
While analyzing the AvBER vs iterations, we find that for CORDIC it is 0.
DDS supplies multi-channel capability, ideal for implementing an array of Digital Down Converters (DDC) and Digital Up Converters (DUC) -- MAC FIR provides a system-level view of the FPGA multiplier array and constructs a multi-MAC implementation based on the available FPGA master clock frequency and required filter sample rate, significantly simplifying the development of high-performance FIR filters -- CORDIC
provides the user with more control over the implementation of the core, allowing the designer to specify key parameters such as the instantiation of the coarse rotation module, the number of implemented iterations, and the desired internal precision, simplifying the design of the carrier recovery loop in a QAM demodulator Price and Availability