CUT

(redirected from Circuit Under Test)
AcronymDefinition
CUTCut Bank (Amtrak station code; Cutbak, MT)
CUTCentral University of Technology (South Africa)
CUTSee You There
CUTCurtin University of Technology (Australia)
CUTCompact Utility Tractor
CUTSee You Tomorrow
CUTCoordinated Universal Time
CUTSee You Then
CUTComing Up Taller (President's Committee on the Arts and the Humanities)
CUTCentral Unitaria de Trabajadores (Spanish: Confederation of Workers; various locations)
CUTCleveland Union Terminal (Cleveland, OH)
CUTCincinnati Union Terminal (railroad station; Cincinnati, OH)
CUTCentral Única dos Trabalhadores (Brazil)
CUTComparable Uncontrolled Transaction
CUTChicago Underground Trio (band)
CUTC++ Unit Testing
CUTCodec Under Test
CUTCircuit Under Test
CUTCaribbean Union of Teachers
CUTChurch Universal and Triumphant
CUTConsumer Use Tax
CUTContinuous Use Temperature
CUTCable Under Test
CUTControl Unit Terminal
CUTConfederated Union of Workers (Costa Rica)
CUTUnited Labor Central (Chile)
CUTUnitary Workers Central (Paraguay)
CUTCampaign for Unmetered Telecommunications (UK)
CUTCentral Utah Telephone
CUTCoding and Unit Testing
CUTCode and Unit Test
CUTCross Utilization Training
CUTConsumer Use Testing
CUTDr Halo Cut Image (file format extension)
CUTCustomer User Test
CUTChina United Telecommunications, Ltd
CUTIntersection of two direction finding bearings
CUTCarcass, Ultrasound, and Tenderness (cattle breeding program)
References in periodicals archive ?
First, we describe the block diagram of the overall tested system including the circuit under test. Then, the design of a redundancy-based fault-tolerant circuit is covered in the next subsection.
Table 1: Transistor sizing for the circuit under test. Device name W/L ([micro]m) M1,M2 14/0.35 M3, M4 37,8/0.35 Mxx PMOS 19/0.35 Mxx NMOS 7/0.35 Table 2: List of main and redundant nodes.
On the other hand, if the circuit under test is the injection circuit shown in Figure 3(b), the measured current is [i.sub.in] and it is plotted in Figure 6(a) as a function of the applied differential voltage, v, for different values of the applied input voltage [v.sub.in] = [V.sub.inDC].
Electrostatic coupling or interference occurs when an electrically charged object approaches the input circuit under test. At low impedance levels, the effects of the interference aren't noticeable because the charge dissipates rapidly.
Functional testing is a form of black box testing, which does not require the structural description of the circuit under test. It avoids the problem of deterministic test generation using structural information about the circuit under test.
This is the only heat sink provided to the circuit under test. Since the on-wafer measured |P.sub.o~ is typically 0.5 to 0.75 dB less than when the same circuit is chipped, die-attached and re-measured, the backmetal temperature is estimated to be 70|degrees~C during the on-wafer power test.
A DMM, like all measurement devices, must be passive to minimize the effect of the measurement on the circuit under test. When evaluating DMMs, investigate whether the DMM in question is truly passive for the appropriate measurements.
It is powered from the circuit under test and does not require a battery.
Conventional two-wire resistance testing cannot distinguish between the circuit under test and the tester's own cabling that connects to the circuit.
Manufacturers supply probes that connect to a circuit under test through SMA connectors, solder-in contacts and pins.