CCY

(redirected from Clock cycle)
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AcronymDefinition
CCYCurrent Calendar Year
CCYCurrency
CCYClock Cycle
CCYCollectif Cheikh Yassine (French Muslim political organization)
CCYCompacted Cubic Yard (measurement)
CCYCochran, Cochran & Yale (Rochester, NY)
CCYCholecystectomy
CCYCamping Club Youth (UK)
CCYCommission on Children and Youth
CCYCommunity Coalition for Youth (Lansing, MI)
CCYCentre for Children and Youth (est. 1997; University of Northampton; Northampton, UK)
CCYclean cut youngers (UK band)
CCYClub Canin Yonnais (French dog club)
CCYChief Communications Yeoman (UK Royal Navy)
CCYClub des Collectionneurs des Yvelines (French: Collectors Club of Yvelines; Yvelines, France)
References in periodicals archive ?
The unit produces the first result after 35 clock cycles and works as a pipeline, after which each unit can produce new results throughout each clock cycle.
Each state is executed in a clock cycle, all internal processor instructions are developed in 4 clock cycles, except the external ones as shown in Figure 2, the RESET is executed in two clock cycles and the interrupt (INT) is executed in 3 clock cycles.
4 pr1 g0 g1 rst=always 5 ( 6 neg $ (sig g0) /\ (sig g1) 7 ) $ abort $ sig rst 8 --If none of the masters is granted, any 9 --request (not simultaneously) will lead 10--to a grant in the next clock cycle. 11 pr2 g0 g1 r1 rst = always 12 ( 13 prev (neg((sigg0) \/ (sigg1)) /\ (sigr1)) 14 --> (sig g1) 15 ) $ abort $ sig rst Listing 4: Example properties for the AHB-based design.
In the beginning, two blocks with 2 x N items are copied to [R.sub.i] and it involves 2 x N/4 = N/2 clock cycles. Then two blocks are sorted in parallel, which also involves up to N/2 clock cycles.
Static energy consumed within one clock cycle could be expressed as
The value is mainly determined by the desired clock cycle period and the critical path delay.
(2) Second Clock Cycle. The comparison value of the capacitor voltage is recorded to determine the sorting position of the capacitor voltage in the array.
The data enter each sub-memory as 16 pixels each clock cycle from the bottom of the sub-memory.
These registers are clocked by the pipelined pulses with one clock cycle based on the shifted clock pulses as shown in Figure 2(a).
These designs have a similar 1.5 clock cycle delay for transmitting input signals to the output.
With the rising edge of the clock cycle the inputs data are fed to the butterfly's input of the system presented in Figure 1.
In addition, the merging of the two labels is required to be performed in one single clock cycle in order to keep the system clock frequency low as this is essential based on the dominance of the high power consumption in the clock nets [35].