DAPDNA

AcronymDefinition
DAPDNADigital Application Processor/Distributed Network Architecture
References in periodicals archive ?
IPFlex develops high performance, multifunctional dynamically reconfigurable processors (DRP) based on its internationally patented DAPDNA technology.
IPFlex and its partners in the DAPDNA Partner Program together provide optimal solutions for customers in inspection systems, image processing, network security, and high performance computing.
IPFlex DRP, based on DAPDNA technology, is a market leader in the next generation processor architecture.
Tata Elxsi, one of the largest product design and embedded services firms in the world, servicing customers in a wide range of industries, joins the DAPDNA Partner Program along with 15 other partners that are already part of the program.
The FFT development kit is the first product that the two companies have co-developed since Sobal joined the DAPDNA Partner Program.
About the DAPDNA Dynamically Reconfigurable Processor
The DAPDNA-EP100 serves as the primary board of the DAPDNA Ethernet Platform.
DAPDNA-DVI is an interface board that connects DVI monitors to the DAPDNA evaluation boards.
The company is also working on an additional feature that allows execution, evaluation and debugging of applications on DAPDNA evaluation boards directly from Simulink in real-time for users familiar with MATLAB/Simulink tools.
Dynamically reconfigurable processor based on DAPDNA is designed as a dual-core processor comprised of a high-performance RISC core and a dynamically reconfigurable processor core, and it is a platform that provides hardware performance while maintaining software flexibility.
The company's DAPDNA technology enables systems described in software languages, such as C, to be implemented in silicon devices with performance equivalent to custom-designed chips, with a combination of its FW II design tool and the DAPDNA-2 dynamically reconfigurable processor.
IPFlex's DAPDNA architecture addresses the difficulties in building these systems by providing a high performance architecture that is easily understood and employed by algorithm designers.