In this category, the leakage current reduction through incorporation of LECTOR technique in dynamic DCVSL circuits is demonstrated.
It is observed that dynamic DCVSL gates based on the first architecture are 1.6 to 1.4 times faster than the conventional dynamic CVSL circuits.
Sanchez-Sinencio, "A DCVSL delay cell for fast low power frequency synthesis applications," IEEE Transactions on Circuits and Systems.
Singh, "A low voltage high speed DCVSL based ring oscillator," in Proceedings of the Annual IEEE India Conference (INDICON '15), pp.
The key reason for DCVSL gate having abnormal short-circuit power is the noncomplementary output nodes turning on the two PMOS transistors simultaneously.
We summarize the general procedure for how to analyze the HT detection probability in DCVSL systems through abnormal power observation.
In order to create an erroneous output in DCVSL, a HT has to make one or more of the inputs noncomplementary.
Table 2 shows the ratio of the total number of abnormal power peaks over the total number of all input patterns for various basic DCVSL gates.
The area for DCVSL modules was obtained from customized layout in Virtuoso.
We implemented a 64-bit full adder using CMOS and DCVSL in Cadence Virtuoso.
CMOS circuits have more PMOS transistors than the DCVSL version.
To address this need, we propose to use the inherent characteristic of DCVSL to detect HTs at runtime, without requiring a golden chip and a large number of test vectors.