In the proposed DETDFF If CLK=O and data input DIN=1, then both the NMOS in the INV2 inverter circuit are ON, and hence the node X is pulled down to 0.
Three stage Asynchronous micropipelines using the proposed DETDFF has been simulated and its performance is compared with the asynchronous micropipelines constructed using DETDFFs by Gago, WaiChung and Tin Wai Kwan.
The results shows that the Micropipeline implemented using the proposed DETDFF stands ahead in power consumption and delay compared with Micropipelines using Gago WaiChung and T.
13[micro] based micropipeline using the proposed DETDFF.
As the power consumption is more or less independent of frequency, the micropipeline using current mode logic DETDFF will be more appropriate for multi GHZ frequencies.
The results shows that the Micropipeline implemented using the proposed DETDFF has low power consumption and lower delay compared with Micropipelines using other DETDFFs.