The results shows that the Micropipeline implemented using the proposed DETDFF stands ahead in power consumption and delay compared with Micropipelines using Gago WaiChung and T.W.Kwan DETDFFs in both 0.13[micro] and 0.18[micro] CMOS technologies.
Figure 7 shows the simulation output for the three stage 0.13[micro] based micropipeline using the proposed DETDFF. 20 bits of alternate is and Os are transferred through the micropipeline and from the wave forms we can see that the data bits are moving from one stage to another at each edge of Rin(Request) signal.
As the power consumption is more or less independent of frequency, the micropipeline using current mode logic DETDFF will be more appropriate for multi GHZ frequencies.
On replacing traditional latches by DETDFFs, will eliminate the need of phase converters.
Designing of asynchronous Micropipelines using DETDFFs have been discussed in  and  and in this paper an attempt have been made to construct asynchronous micropipeline using the proposed double edge triggered D Flip Flop with an aim to achieve low power consumption and delay.
The next section gives brief description about the design and operation of the previously reported DETDFFs.