DPLL


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AcronymDefinition
DPLLDigital Phase-Locked Loop
DPLLDavis-Putnam-Logemann-Loveland (search algorithm)
DPLLDeer Park Little League (Texas)
DPLLDiscrete-Time Phase-Locked Loop
DPLLDysimmune and Pseudo-Lymphomatous Lymphadenopathies
References in periodicals archive ?
The proprietary jitter shaping, cleanup, and filtering techniques in the ZL30105 DPLL - resulting in 600 ps (picoseconds) of worst-case unfiltered peak-to-peak jitter and exceeding stringent OC-3 jitter requirements - enables its use in tandem with a Zarlink frequency multiplying analog PLL to produce even higher line rate clocks, with low combined jitter, than those supported by the device's 19.
there is a trade-off between the effort spent on consistency and that spent on subsequent DPLL search.
Holdover mode--the DPLL constantly calculates the average frequency of the locked reference.
The T4 DPLL is a simplified version of the T0 DPLL, and is specifically used for frequency conversion.
Any input reference can be fed with Sync (frame pulse) or clock and each of the DPLLs can be programmed to synchronize to sync pulse and sync pulse/clock pair.
It is six times smaller than discrete PLLs and two times smaller than competitive DPLL solutions.
110 digital switch family by introducing the ZL(TM)50031 TDM (time division multiplex) digital switch with an integrated Stratum 4E DPLL (digital phase locked loop).
DPLL (digital phase locked loop) provides best combination of features, jitter performance and small size for high-speed networks
DPLL (digital phase locked loop) family provides maximum flexibility, superior performance, and full range of features for wide range of equipment needs
The ZL30362 has four highly programmable multi-function DPLLs, coupled with four independent synthesizers capable of generating multiple independent frequencies to directly drive both 1 Gigabit Ethernet (GbE) and 10GbE physical layers (PHYs).