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Reference monitoring--the DPLL needs to constantly monitor quality of its input references.
Narrow loop bandwidth--the DPLL can be viewed as a phase noise filter.
High jitter and wander tolerance--the DPLL should tolerate large phase noise at its input and still maintain synchronization.
Timing card DPLL references can come externally from a Building Integrated Timing Supply (BITS) or internally from line cards.
In this case, an additional low-cost wideband DPLL is needed to convert the frequency of the line card extracted clock to the frequency needed by T1/E1/CC Line Interface Units (LIU).
In this case, the timing card DPLL is synchronized to one of the extracted line clocks.
Each DPLL usually drives common clock frequencies such as 8 kHz (DS0), 1.
The T4 DPLL is a simplified version of the T0 DPLL, and is specifically used for frequency conversion.
Both the T0 and T4 DPLL have output APLLs that multiply the clock rate and simultaneously attenuate jitter.
We can not describe DPLL in simple terms; it performs a backtracking, depth-first search through the space of partial truth assignments, using unit-clause and pure-literal heuristics (figure 14).
An especially promising new method, reported in Gomes, Selman, and Kautz (1998), exploits the fact that the time required by the DPLL procedure is highly dependent on the choice of splitting variable, producing a heavy-tailed distribution of running times (figure 16).
Majercik and Littman (1998a) describe a planning compiler based on this idea and present an E-MAJSAT solver akin to DPLL.
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