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DXData Exchange (used by OPC foundation OLE for Process Control)
DXData Explorer
DXDirector's Cut
DXDirect Expansion (refers to refrigerant-type cooling coils ie DX coil)
DXDeus Ex
DXDigital Experience
DXDirect X
DXDesign Exchange
DXDeal Extreme (online shop)
DXDocument Exchange
DXDeveloper Experience (software)
DXDriver Class
DXD-generation X
DXData Extraction
DXDirect Exchange
DXData Register
DXDegeneration x (WWE wrestling)
DXDelta Chi (fraternity)
DXLong Distance Communications (radio)
DXDirectory Exchange
DXDigital Cross Connect
DXDigital Index (35mm film encoding)
DXDigital Exclusive (Nikkor lenses)
DXDirectorate for External Relations (US DoD; Defense Intelligence Agency)
DXBipack (cinematography)
DXDistance Unknown (long-distance radio reception)
DXDragon Expo
DXDomestic Extemporaneous Speaking (debate)
DXDirectory of Expertise (USACE)
DXDuplex Signaling
DXDepth Excess
DXDitch Crossing (pipeline route)
DXDiscreteLogix (Islamabad, Pakistan web developers)
DXDynamic Exfiltration (Cytec Corporation/ATK-Thiokol emergency personnel evacuation technology)
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References in periodicals archive ?
If we re-used the ARM NEON SIMD data register, which was the result data right before the operation as operand data at the next operation during NEON SIMD programming, it has data dependency, and data dependency causes a Read After Write (RAW) data hazard (aka, stall) which takes some clock cycles to load data that was result data right before operation again.
DQ15--DQ0 Data input/output Sector erase, A11--A19 used to select sectors; CE# Chip enable Write cycle data within the internal latch OE# or CE# for high output for the three state read cycle output data, write cycle input data OE# Output enable CE# start work for low time start WE# Write enable Gating signal of data output buffer VDD Power Supply Control write operation V SS land Supply power supply: 2.7 - 3.6V Table 3--K9F2808 instruction and timing function First Second Busy time cycle cycles acceptable command Read data register (data area) 00H/01H -- Read data register (free area) 50H -- Read device ID 90H -- reset FFH -- O Write data 80H 10H Block Erase 60H D0H Read state 70H -- O
The flow of data to the instruction register (IR) and the data register (DR) is controlled by the test mode select (TMS) with a 0 or 1 bit to move from one state to another state, while the TCK synchronizes the 16-state machine operation.
The modular arithmetic unit embedded in this chip operates on integers of up to 1024 bits wide and reads operands from the data register file, operates on them, and writes the results back to the data register file.
Victimization data register on the surface deeper structural realities which reproduce observable phenomena.
So-called zero-bit data register (DR) scans (ZBS) are counted to determine the intended control level.
Additionally, an internal data register stores the currently displayed data.
This requirement is met by providing shadow flip-flops (FFs) in the scan path before each RAM address bit and control bit FF along with just one shadow data FF for the full RAM data register.
For example, typical NAND flash devices program 528 B at a time from an internal data register of the same size--512 B being the size of a hard disk sector with 16 B added for error correction.
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