DBE

(redirected from Double Bit Error)
AcronymDefinition
DBEDisadvantaged Business Enterprise
DBEDeutsche Biographische Enzyklopädie (German: German Biographical Encyclopedia)
DBEDame Commander of the Order of the British Empire
DBEDatabase Engine
DBEDouble Balloon Enteroscopy (bowel procedure)
DBE1,2-Dibromoethane
DBEDouble Buffer Extension (computing)
DBEDaughters of the British Empire
DBEDeutsche Gesellschaft zum Bau und Betrieb von Endlagern (German society for building and maintenance of garbage final storage places)
DBEData Base Engine
DBEDouble Bit Error
DBEData Bus Enable
DBEDynamic Bass Enhancement
DBEData Base Environment
DBEDame of the British Empire (honorary title; UK)
DBEDigital Business Ecosystem (software)
DBEDeep Breathing Exercises (therapy)
DBEDepartment of Border Enforcement (Iraqi border guards)
DBEDisabled Business Enterprise
DBEDevelopment Bank of Ethiopia (est. 1994)
DBEDigital Back-End (computer platform)
DBEDirektoratet for brann- og eksplosjonsvern (Norwegian: Directorate for Fire and Explosion Prevention)
DBEDe Bene Esse (Latin: Of Well Beign; law)
DBEDiploma Básico de Español (Spanish: Basic Spanish Diploma)
DBEDespatch Payable Both Ends (shipping)
DBEDirectorate of Border Enforcement
DBEDesign Basis Earthquake
DBEDominet Bank Ekstraliga (Polish basketball league)
DBEDécor Bois Extérieur (French: Outdoor Wood Decor)
DBEDFAS Business Evolution
DBEDepartment of Business and Employment (Australia)
DBEDigital Broadcast Equipment, Inc. (Texas)
DBEDesign-Basis Event
DBEDon't Be Evil
DBEDouble Bond Equivalent
DBEData Bus Element
DBEDegenerate Band-Edge (photonic crystal)
DBEDouble Below Elbow (amputation)
DBEDistorted-Wave Born Exchange
DBEDepartmental Budget Estimate
DBEDynamic Bias Estimator
References in periodicals archive ?
It ensures data integrity by also detecting the probabilistically very rare occurrence of a double bit error that the old parity scheme cannot detect and thus "bullet proofs" hot plug and hot swap procedures that are now becoming standard in this market.
The PRIMERGY S3 generation reportedly supports dual-core Intel Xeon processors with VT technology; a separate, independent second bus included in the chipset (up to 1.333GHz) for each processor; new fully buffered DIMMs (FBDIMMs) providing a high-bandwidth, large-capacity channel solution; enhanced ECC (retry double bit errors) and CRC; as well as new SAS (serial attached SCSI) serial hard disk technologies to ensure high system performance.
CRC detects all single bit errors, all double bit errors, all odd number of errors, all burst errors up to 32bits long, and has a -2-32 rate of undetected random error patterns.