EREW

AcronymDefinition
EREWExclusive Read Exclusive Write
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References in classic literature ?
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[1986] have proven that the latter requires [Omega](log n) time on the CREW or EREW PRAM no matter how many processors are used.
Based on new insight into the structure of minimum spanning trees, we show that this paradigm can be implemented on the EREW, solving the MST problem in O(log n) time using n + m processors.
Notice that EREW algorithms are actually more practical in the sense that they can be adapted to other more realistic parallel models like the Queuing Shared Memory (QSM) [Gibbons et al.
We choose the EREW PRAM as our ideal architecture since its behavior resembles that of a real system when ignorign the effects of interconnection networks and caches.
We define scalability [Psi](s) of an architecture for a given algorithm with problem size s as the ratio of the algorithm's asymptotic speedup on the architecture in question and its corresponding asymptotic speedup on an EREW PRAM.
(1) Specifically, we use an exclusive read, exclusive write (EREW) PRAM, which is an idealized model of a parallel computer that satisfies all nonconflicting memory accesses in one cycle and queues conflicting memory accesses to be satisfied one after another, each requiring one time unit [7].
We now return to the question of efficiently emulating an EREW PRAM on a c-collision crossbar.
If k = n and c = O(1), we can conclude that any scheme based on a single hash function requires [Omega](lg n/lg lg n) time to emulate one step of the EREW PRAM.