FD-SOIFully Depleted Silicon-On-Insulator (MOSFET type)
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And in still other presentations, Bernd Srocka, Ph.D., vice president of engineering at Unity SC, described ultra-thin double-layer metrology with high lateral resolution with applicability to FD-SOI substrates.
The SoC is built with 28 nm FD-SOI technology to reduce soft errors and increase MTBF.
Because of the ultra-thin layer in FD-SOI, the biasing creates a buried gate below the channel making the transistor act as a double vertical gate transistor.
ST's planar FD-SOI technology constitutes a cost-effective solution, allowing the Company to offer fully depleted devices at the 28nm node, well in advance of others in the industry.
announced that its custom and analog/mixed-signal (AMS) IC design flow has achieved certification for Samsung Foundrys 28nm FD-SOI (28FDS) process technology.
"This collaboration between Leti and Keysight will strengthen the global FD-SOI ecosystem by providing an automatic extraction flow for building model cards associated with the Leti-UTSOI models, which already are available in all the major SPICE simulators," said Marie Semeria, Leti's CEO, in a press release.
Rambus Inc (NASDAQ:RMBS), a technology solutions company, signed a license agreement with STMicroelectronics (NYSE:STM) that covers Cryptography Research (CRI) and Memory and Interface technologies for inclusion into STMicroelectronics products and collaboration on its Fully Depleted Silicon On Insulator (FD-SOI), the company disclosed on Monday.
Synopsys, Inc today announced that GLOBALFOUNDRIES (GF) has certified the Synopsys Design Platform for the GF 22nm FD-SOI (22FDX) process, ensuring designers achieve optimized implementation and predictable signoff results using industry leading digital design tools.
The Swiss group will continue to be the venture's supply-chain partner and provider of advanced process-technology partner (FD-SOI) and application-processor IP.
The collaboration enables Synopsys' tools to enhance support for differentiating GLOBALFOUNDRIES FD-SOI design features, including support for the adaptive body bias that unlocks FDX SoC performance and ultra-low-power operation, while lowering barriers of migration from bulk nodes.
Following an evaluation using a multi-million-gate FD-SOI SoC design, TetraMAX II demonstrated an order of magnitude speedup in runtime and significant test-pattern-count reduction without impacting test coverage.
CMP s clients also have access to 28nm FD-SOI and 130nm SOI (Silicon-On-Insulator), as well as 130nm SiGe processes from STMicroelectronics.