FD-SOI

AcronymDefinition
FD-SOIFully Depleted Silicon-On-Insulator (MOSFET type)
References in periodicals archive ?
Our broad collaboration with GLOBALFOUNDRIES has been focused on delivering the platform and IP needed for seamless adoption of the FD-SOI technology at 22 nanometers and smaller geometries," said Michael Jackson, corporate vice president of marketing and business development for Synopsys' Design Group.
ST's planar FD-SOI technology constitutes a cost-effective solution, allowing the Company to offer fully depleted devices at the 28nm node, well in advance of others in the industry.
With the recent announcement of the company's next-generation 12FDX technology, the FDXcelerator Partner Program builds upon GLOBALFOUNDRIES' industry-first FD-SOI roadmap, a lower-cost migration path for designers desiring advanced node design.
This collaboration between Leti and Keysight will strengthen the global FD-SOI ecosystem by providing an automatic extraction flow for building model cards associated with the Leti-UTSOI models, which already are available in all the major SPICE simulators," said Marie Semeria, Leti's CEO, in a press release.
About 300 projects have been designed in ST s 90nm process, more than 350 in bulk 65nm, and already over 50 projects prototyped in 28nm FD-SOI.
Developed over a multiyear partnership with ST, the design flow allows concurrent area, power and timing optimizations to allow engineers to optimize their designs for the ST 28-nm FD-SOI process.
The agreement, on 28nm FD-SOI technology, encompasses ST s fully developed process technology and design enablement ecosystem.
UTBB FD-SOI technology is ST s Faster, Cooler, and Simpler solution: it delivers significant improvements in performance and power savings while minimizing adjustments to existing design and manufacturing methodologies.
These process technologies include leading-edge bulk CMOS and the faster, cooler and simpler FD-SOI (Fully-Depleted Silicon on Insulator) technology that offers outstanding performance at geometries of 28nm and below.
As per ST, when incorporated into the products made utilizing ST s FD-SOI, Memoir s Algorithmic Memories supply uncompromised performance under the outcome of FD-SOI s recognized power and performance advantages.
Nano2017 strengthens ST s leadership in key technologies: FD-SOI (low-power, high-performance processing), next-generation imaging (sensors and image signal processors) and next-generation embedded non-volatile memories.
With this, Rambus will be able to benefit from FD-SOI s reduced silicon geometries and lower power consumption at 28nm and below in its future memory and interface solutions.