is being used to make chips for mobile phones, and much of the electronics used in automobiles and aerospace applications will soon be packaged in this way," says Gotro.
The market for semiconductor lithography equipment with greater FOWLP functionality continues to expand, reflecting increased demand for high-density redistribution layer wiring that requires high-resolution lithography.
The FPA-5520iV HR Option maintains the same basic functionality, performance and productivity of the FPA-5520iV stepper (released in July 2016) for FOWLP processes while delivering a higher resolution of 0.8 m.
Orbotechs Emerald UV Laser Drilling solution is one of the key processes available in the FOWLP joint lab development line.
The FOWLP development line at IMEs facilities at Singapore Science Park II, and its new facilities at Fusionopolis Two, will allow IME and its partners to develop technologies that will serve a wide range of markets including consumer electronics, healthcare and automotive.
FOWLP is considered a key technology platform for system scaling, enabling multiple chips to be integrated in a small form factor on a single package.
The Centre undertakes complex multi-disciplinary research to develop new innovations in advanced packaging including bump, TSV, 2.5D interposers and now FOWLP. Through its work at the Centre, Applied Materials has developed technology that has been successfully implemented in several of its semiconductor equipment products.
The new lithography tool offers improved Fan Out Wafer Level Package (FOWLP) functionality and is designed to help users enhance their productivity.
FOWLP technology has attracted attention as a next-generation packaging technology to meet this demand.
In 2016, TSMC's fan out wafer-level package (FOWLP
) for the A10 application IC for Apple will have some impact on flip-chip CSPs, which will make the substrate business uncertain.
Fan-out wafer level packaging platform (FoWLP
) is developed by Samsung that will be valuable for future mobile chipsets and will compete with TSMC chip orders.
To reach the goal of <0.8mm, some companies are expected to use an FOWLP
for the logic device in the bottom PoP.