FinFET


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AcronymDefinition
FinFETFin-Shaped Field Effect Transistor
References in periodicals archive ?
This paper proposed a comprehensive method to optimize the parameters for the Dual Threshold (DT) IG FinFET to obtain the better performance.
Choi, "Dopant-segregated schottky source/drain FinFET with a NiSi FUSI gate and reduced leakage current," IEEE Transactions on Electron Devices, vol.
leadership IP suppliers that can bring 28G backplane SerDes in advanced FinFET
This arms yield, product, and failure-analysis engineers with an effective tool that simplifies the tasks of locating defects and identifying systematic defects of the type that is on the rise in FinFET processes.
The difficulties arise with the FinFET technology is that, FinFET structures experiences signicant self-heating and the operating temperature in FinFET circuits varies directly with number of times the switching activity takes place.
Jong Shik Yoon, executive vice president and head of foundry business, Samsung, added: "We are pleased to have the opportunity to work closely with Qualcomm Technologies in producing the Snapdragon 835 using our 10nm FinFET technology.
As well as the implementation of the advanced 14nm FinFET process, Samsung's innovative packaging technology, SiP(system-in-package)-ePoP(embedded package-on-package), enables the Exynos 7270 to feature outstanding performance and energy-efficiency within a compact solution optimized for wearable devices.
TEHRAN (FNA)- The South Korean tech giant is widening the application of its touted 14-nanometer FinFET process to midrange phones as it attempts to stay ahead of rivals.
WORLDWIDE COMPUTER PRODUCTS NEWS-January 14, 2016-Samsung commences mass production of second generation 14nm FinFET Logic process technology
Technavio's market research analysts estimate upcoming trends, such as the adoption of fin-shaped field effect transistor (FinFET) architecture, which is driven by the growing demand for smart electronic devices such as smartphones, digital cameras, notebooks, PCs, PDAs and tablets.
As critical device dimensions have evolved to the sub-20-nm regime, CMP processes control of within-chip thickness variation after CMP needs to be less than 50 [Angstrom] in polishing the most advanced polysilicon semiconductor devices using FinFET and High K metal gate (HKMG) technology.