GDSII


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AcronymDefinition
GDSIIGraphic Design System II
GDSIIGraphic Database System Information Interchange
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References in periodicals archive ?
To solve this design problem, we have developed a computer-aided design (CAD) software package for scripting and streaming complex shapes to GDSII. The Toolbox utilizes the freely available Java based (JGDS) library for encoding shapes to GDSII objects [13].
It is assumed that the FIB instrument is equipped with a digital pattern generator and that the lithography patterns are presented in GDS, GDSII, or a similar format that is conventional for transferring layout designs between different fabrication equipment.
the layout of the soft core itself could be fixed in a GDSII file
Certain that Fujitsu's designs would now meet the required timing specifications, the TI-Magma design team was able to quickly take the complex designs from netlist to clean GDSII without struggling through numerous synthesis-to-layout iterations.
The Lynx Design System takes full advantage of the latest Galaxy enhancements, including: Low power implementation flow including concurrent multi-corner, multi-mode (MCMM) optimization and analysis with support for IEEE 1801 standard Design Compiler[R] Graphical physical guidance to IC Compiler that tightens timing and area correlation for a faster, predictable and convergent path from RTL to GDSII IC Compiler Zroute DFM-optimized router and In-Design DRC auto fixing with IC Validator, dynamic rail analysis with PrimeRail, and final stage leakage reduction that preserves timing
The complete GDSII view of the PHY is licensed directly from SMSC.
In addition to ANF output, NETEX-G can create a GDSII stream file that can be read into IC design software so that the chip and the IC package can be simulated as a complete system.
The methodology is incorporated across the complete Cadence RTL to GDSII flow, which includes Encounter RTL Compiler, Encounter Conformal Low Power, Encounter Digital Implementation System, Encounter Timing System, Encounter Power System, Cadence QRC, Cadence CMP Predictor and Cadence Physical Verification System.
The company supplies tools that predict semiconductor yield from design layout and tools to enhance the Graphic Design System II (GDSII) layout to make it more manufacturable.
EM3DS also includes GDSII and DXF translators allowing the simulator to reuse the design of other sources, or simply using external editors.
The register transfer level (RTL) to GDSII reference design flow shortens time-to-market for ARM core-based designs.