HLDDHigh Level Design Document
HLDDHigh-Level Decision Diagram
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The HLDD model is created from the instruction set, and it represents the high-level structure of the microprocessor.
We propose a formal method to automate the test program generation for microprocessors using high-level decision diagrams (HLDD) [14,15] as a diagnostic model.
Section 2 presents the mathematical basis that supports the HLDD theory.
For modelling of F we will use the behavioural level HLDD model.
Each BDD is HLDD as well, with two terminal vertices labelled by constant functions 0 and 1, and D(x) = {0, 1} for every variable x.
Now it is easy to get an algebraic expression for the HLDD function [f.sub.k].
There are two ways to generate an HLDD for some digital system: one based on procedural description and another based on iterative superposition.
Suppose an HLDD, containing a chain of non-terminal nodes labelled by variables [x.sub.0], [x.sub.1], ..., [x.sub.k], [x.sub.0], was transformed in the following way:
Different from the well-known Reduced Ordered BDD models, which have worst-case exponential space requirements, HLDD size scales well with respect to the size of the RTL code.
Figure 3 presents a functional segment of VHDL description of an example design CovEx2 and its corresponding HLDD representation.
We distinguish three types of HLDD representations according to their compactness and with consideration of the HLDD reduction rules.
HLDD reduction rule 1: Eliminate all the redundant nodes whose all edges point to an equivalent sub-graph.