On the other hand, each HLDD node can be regarded as a hypothetical structural unit of the microprocessor, exercised by a corresponding instruction.
Because of this one-to-one mapping between the nodes in HLDDs and the corresponding high-level functional units, we can use the HLDD nodes as a checklist for high-level test planning and organization of test programs for microprocessors.
Each path in an HLDD describes the behaviour of the system in a specific mode of operation (working mode).
The HLDD based fault model for microprocessors includes three fault classes: D1: The output edge of anode m for z(m) = v, v[member of] V (z(m)) is always activated; notation: z(m)/v; (it is similar to the logic level stuck-at fault (SAF) z/1 for the line z);
Now it is easy to get an algebraic expression for the HLDD function [f.
There are two ways to generate an HLDD for some digital system: one based on procedural description and another based on iterative superposition.
Suppose an HLDD, containing a chain of non-terminal nodes labelled by variables [x.
Input: HLDD G Output: The set of characteristic polynomials for G we shall evaluate polynomials node by node.
Consider the example of HLDD representation of a VHDL design, containing feedback loops shown in Fig.
Different from the well-known Reduced Ordered BDD models, which have worst-case exponential space requirements, HLDD size scales well with respect to the size of the RTL code.
Figure 3 presents a functional segment of VHDL description of an example design CovEx2 and its corresponding HLDD representation.
We distinguish three types of HLDD representations according to their compactness and with consideration of the HLDD reduction rules.