HNNS

AcronymDefinition
HNNSHrvatski Nacionalni Nogometni Savez (Croatian: Croatian National Soccer Federation of Canada and USA)
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References in periodicals archive ?
The FPGA-based HNN's digital system developed is depicted in Figure 1 and consists of a control unit (CU) and a data flow (DF) which implements the processes shown in the block diagram of Figure 2.
From Figure 4, it can be noticed that the proposed system implements the asynchronous version of the HNN, since the weight unit is designed in order to compute one weighted value ([WY.sub.i]) at a time.
This section presents the set of experiments conducted in order to obtain some relevant parameters of the HNN implementation on FPGA, such as, maximum operating frequency and chip-area occupancy, in function of the quantity of neurons.
Figures 9 and 10 depict two stable states stored by the HNN (left side of the pictures) and the prompting inputs applied to the network with some corrupted bits (right side of the pictures).
On the other hand, an interesting observation is that the chip-area utilization does not always increase according to the enlargement of the network size; it also depends on other variables, as the weight matrix and the number of stored patterns of the HNN. The present purpose allows the implementation of larger networks on the chip by properly setting such parameters.
In Section 3, a delayed fractional-order HNN with two neurons is proposed.
Bifurcation and Chaos in Delayed Fractional-Order HNN