IP3SIntegrated Process Planning/Production Scheduling
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Although previous works have shown that specially designed spiked- or delta-doped MESFETs can result in record IP3/[P.sub.DC] ratio figure of merits,[3-5] the present work aims to reduce the cost, weight, size and integration complexity of the basic receiver RF chain by employing HBT technology to provide monolithic DC bias regulation while maintaining high IP3 compared to conventional HEMTs.[1] Typically, off-chip silicon regulators are required to bias both HEMT and HBT amplifier ICs.
HBT technology can provide an elegant solution by integrating both of the bipolar IC regulators onto the HBT high IP3 amplifier MMIC, as shown in Figure 2.
A block diagram of the chip that integrates a two-stage, 9 to 21 GHz, HBT high IP3 amplifier MMIC is shown in Figure 5.
The size and bias were selected based on gain, bandwidth, IP3 and reliability considerations.
In order to derive the IP3 of the back-end, [x.sup.A] must be expanded in polynomial form.
Note that the simplified DC-ADGC receiver back-end input IP3 (IIP3est) expression listed above is a function of the input power.
Representative SFDR curves of a DC-ADGC receiver with 0.5 and 5 percent mismatched digital antilog functions are plotted along with the SFDR curves of a benchmark receiver with a high IP3 and a poor IP3 final analog stage.
Also note that the benchmark receiver SFDR at the minimum input signal level depends largely on the final analog stage IP3. However, as the input signal level increases, the noise figure of the benchmark receiver increases with it and starts to reduce the SFDR.