IS

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Related to Instruction set: Instruction set architecture
AcronymDefinition
ISInformation System(s)
ISIn Service
ISInternet Service
ISInformation Services
ISInternational System (of units)
ISInternational Standard
ISIndustry Standard
ISImage Size (semiconductor manufacturing)
ISInformation Security
ISInternational Staff (NATO)
ISIsland
ISInternet Solutions (South Africa)
ISImage Studio
ISInternet Society
ISIndian Standards
ISIsrael (Including Israel-Jordan & Israel-Syria Demilitarized Zones)
ISIndustrial Safety
ISIndustrial Society
ISIndustrial Security
ISInstruction Set
ISInformation Structure (linguistics)
ISIncome Support (UK)
ISInternal Security
ISInternal Stop
ISInternal Standard
ISInstallation Survey
ISInitial Study
ISIndustry Sector
ISIntegrated System
ISIntegrated Science
ISIrish Standard (fire alarms)
ISIntegrated Schedule
ISIndustrial Specialist
ISIntelligent Services Gateway
ISIntelligence Specialist (Navy Rating)
ISIntelligent Systems (IEEE International Conference)
ISIntelligent Sport (Lexus model)
ISInfrastructure Service
ISInternational Supplement (ODT)
ISIceland
ISIndianapolis Star (newspaper)
ISIntermediate School
ISIntermediate System
ISIron Soldier (Atari Jaguar game)
ISInsertion Sequence (molecular biology)
ISInterface Specification
ISInternal Specification
ISIntelligent Sensor
ISInvestigations Service (OPM)
ISInner Sphere (Mech Warrior)
ISInterstate System
ISImportance Sampling
ISInterim Standard (series of communication standards)
ISInterim Status
ISIslamic State
ISInstrumentation System
ISImagery Server
ISInteger Sort
ISInterrupt Status
ISIntelligence Squadron
ISInstallshield
ISInitial Spares
ISImperial Stout
ISIndexed Sequential
ISInformation Superiority
ISImage Stabilization (camera feature)
ISInspection Services
ISImage Shack (image hosting service)
ISIntrinsic Safety
ISInternational Standardization
ISImage Stabilizer (camera lens)
ISInformation Separator
ISInduction Soldering
ISIsles of Scilly (UK)
ISInfinite Stratos (Japanese novel series)
ISIasi (Romania)
ISInternational Socialists
ISIndentation Strength
ISIntrinsically Safe
ISInbred Strain
ISInterscope Records (record label)
ISIsotope Separation
ISIpecac Syrup
ISIlta-Sanomat (Finnish newspaper)
ISImpôt sur les Sociétés (French: corporation tax)
ISImmunosuppression (treatment complication)
ISIron Savior (band)
ISIsmailia (Egyptian automobile license plate)
ISInfrasound
ISInduced Sputum
ISInfraspinatus (muscle)
ISIsernia, Molise (Italian province)
ISIntercostal Space
ISIncentive Spirometer
ISInvestigation Scientist (US NASA)
ISInventory of Systems
ISIndicating Switch
ISInterferon Sensitivity
ISIsotopic Source
ISInstituti I Statistikes (Albanian: Statistics Institute)
ISInternal Silencer
ISInfinite Spawn (gaming)
ISInstituto Sertão (Brasil)
ISImtiazi Sanad (Certificate of Distinction Pakistan Armed Forces)
ISImmaculata Symphony (Immaculata, PA)
ISItakura-Saito distortion
ISInvestments Equal Savings (macroeconomic curve)
ISInsurgent Sisterhood (Star Wars Galaxies guild)
ISIndustry Solutions Module
ISImmersible Switch
ISInteractive Structures, Incorporated
IS(USN Rating) Intelligence Specialist
References in periodicals archive ?
The CLIPPER instruction set is fairly conventional and reflects the experience of its designers with respect to two factors: what is needed for convenient and efficient programmability, and what can be easily implemented in hardware.
The following section presents the entire instruction set for CPUSIM and the corresponding microinstructions for execution.
Padegs The best examples of that are in the floating-point instruction set. We initially defined floating point such that overflow resulted in an unpredictable value; models could vary as to what they provided for the result value on overflow.
The MULTI Development Environment for the ARM core, including a C/C++ compiler, assembler, linker, and instruction set simulator, costs $5900 (single-seat developer's license) for a node-locked license, and $8900 for a floating license.
According to the company, the new MIPS32 M14K and M14Kc cores are the first MIPS32-compatible cores that also execute the new microMIPS instruction set architecture (ISA).
By comparison, competitive architectures either prohibit designer-defined extensions or require the designer to manually adjust compilers, assemblers, debuggers, operating systems, instruction set simulators, co-verification models and EDA implementation scripts when user-defined hardware changes are made to the processor RTL.
graphics instruction set as an alternative to Intel's new Katmai instructions.
The RXv2 core is backward compatible with the Renesas RXv1 CPU core employed in the existing RX family of 32-bit CISC (Complex Instruction Set Computer) microcontrollers (MCUs).
The Thumb-2 instruction set combines 16- and 32-bit instructions to improve code density and performance.
The AMD Opteron processor, with the "Hammer" core, is a 64-bit processor that builds upon the x86 instruction set and can also fully support 32-bit computing.
Hitachi says it's unlikely to produce a mixed instruction set but will converge the base technologies at least to the point where the CPUs will present a common interface to the back-end.
It is a Pentium-class CPU with an x86-native instruction set and 32 KB of integrated L1 cache that efficiently runs Windows CE, WindowsXP embedded, Linux and other x86-compatible operating systems.
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