They offer a broad range of output types including LVCMOS
, LVPECL, LVDS, and HCSL.
The P3P8203A LVCMOS
peak EMI reduction clock generator targets applications such as graphics cards, computing and consumer applications.
2] THT enclosures in base station and SDH/SONET applications, and offers LVCMOS
and sine wave output.
NASDAQ: SLAB), a leader in high-performance, analog-intensive, mixed-signal ICs, today introduced the industry's first universal clock buffers capable of replacing LVPECL, LVDS, CML, HCSL and LVCMOS
buffers with a single IC, eliminating the need for multiple fixed-format buffers.
The family supports 12 single-ended clock outputs, as well as 8 differential output pairs that can be configured as HCSL, LVPECL, LVDS, CML or LVCMOS
2 V and I/O capacities ranging from 86 to 358 pins that support LVCMOS
, SSTL, HSTL and LVDS.
Eliminating the need for multiple clock generators and/or buffers, the device's outputs support any combination of four differential outputs or up to eight LVCMOS
The 5P49V5901 s four universal output pairs are each independently configurable as HCSL, LVPECL, LVDS, or dual LVCMOS
3 V operation, LVCMOS
or clipped-sinewave output logic and jitter of <1 pS rms.
The new P3MS650100H and P3MS650103H LVCMOS
peak EMI reduction clock generators are ideal for use in space constrained applications such as portable, battery powered devices -including mobile phones and tablets where EMI/RFI can be a significant challenge and compliance with regulations is a pre-requisite.
The Pb-free RoHS-compliant devices perform with a LVCMOS
or HCMOS output logic and jitter of <1 pS rms over voltages of 3.
A number of blocks in FPGAs from Xilinx, for example, can switch from LVDS or HSTL (high-speed transceiver logic) mode to temporarily act as LVCMOS
(low-voltage CMOS) blocks.