LVDS


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AcronymDefinition
LVDSLow Voltage Differential Signaling
LVDSLow Voltage Differential Signal(ing)
LVDSLow Voltage Differential SCSI
LVDSLow Voltage Data Signal
LVDSLow Volume Dissemination System
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References in periodicals archive ?
With the Xilinx Kintex Ultrascale FPGA, LVDS digital I/O and gigabit serial I/O, the Model 71810 becomes an excellent high performance off-load co-processor to fit a wide assortment of processing needs in the most demanding of applications.
In addition to supporting up to 600-Mbps data rates, ADN465x LVDS digital isolators support 300-MHz clocks to enable isolation of precision convertors with LVDS interfaces.
It also provides a full array of connectivity for video output, data transmission and compatible access with peripheral devices, including HDMI, DVI, VGA and LVDS connections, 2 USB 2.0 and 2 USB 3.0 ports, 2 SATAIII connectors, mSATA, Mini PCIe and 2 COM ports.
The company's new LVDS TFT display line-up has various screen sizes including 5.7" VGA, 6.5" VGA, 7.0" WVGA, 8.0" WVGA, 9.0" WVGA and 10.4" SVGA.
Axon' is one of the only manufacturers to offer LVDS screened flat cables with a pitch of 1.00 mm.
The "PROTO" and "EVAL" boards both contain an alphanumeric LCD display and provide CAT5E connectors to demonstrate the high-speed LVDS functionality of the A3P250 (and larger) devices within the ProASIC3/E family.
The ATR0839 enables the oscillator by LVDS signals.
Outputs from the CG635 can be set to standard logic levels including CMOS, PECL, ECL, and LVDS. Offset and amplitude also can be continuously adjusted between -5 V and +5 V.
"Communication system designers expect their silicon vendors to provide reference designs with design-in tips to accelerate time-to-market," said Stephen Kempainen, technical marketing manager for integrated LVDS products at National Semiconductor.
It boasts throughput exceeding 10Gbps utilizing low voltage differential signaling, (LVDS) technology.
The GPIO-1 provides a high-performance 66 MHz PCI interface with up to 256 MB of on-board SDRAM memory and 64 bits of bi-directional I/O signals, with each signal presenting the option of driving or receiving TTL, CMOS, LVTTL, LVDS, GTL or HSTL levels, Additionally, this interface furnishes DMA and interrupt capabilities.