LVPECLLow Voltage Positive Emitter Coupled Logic
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* The Voltage Controlled LVPECL Oscillator outperforms other LVPECL phase noise oscillators.
The 4M-series devices operate with [+ or -]50 ppm frequency accuracy over the wide industrial temperature range of - 40[degrees]C to 85[degrees]C, and support LVDS and LVPECL differential signaling standards at frequencies of up to 625 MHz.
In this work the Virtex-4 FPGA's LVPECL simulation model [7] is used for simulation.
Electrical outputs from the receivers consist of differential CML, LVDS or LVPECL data signals on the Receive (RX+ and RX-) pins and single ended CMOS or LVPECL signal detect functions with output squelch on the Signal Detect (SD) pins.
They offer a broad range of output types including LVCMOS, LVPECL, LVDS, and HCSL.
This family is available in a surface-mount package with enable/disable functions and various outputs of LVPECL (V300 series), CMOS (V400 series) and LVDS (V500 series).
Stratix devices support various differential I/O electrical standards such as LVDS, LVPECL, PCML, and HyperTransport, as well as high-speed interfaces, including UTOPIA IV, SPI-4 Phase 2, SFI-4, 10G Ethernet XSBI, RapidIO, HyperTransport, and others.
Each output is individually programmable as LVPECL, LVDS, or as a pair of LVCMOS signals.
Product is offered in 5 volt and 3.3 volt, and packaging is offered in SMD 5 x 7, 5 x 3.2 mm, and other industry standard packages as well as CMOS, LVDS, and LVPECL outputs.
Featuring independently programmable output buffers with independent power rails that allow mix-and-match output formats, the MPS14 supports any combination of LVPECL, LVDS, HCSL and CMOS on its 4 outputs.
The new devices meet clock generation requirements in the latest 2.5 V / 3.3 V low-voltage positive emitter coupled logic (LVPECL) designs for applications in routers, switches, servers, and basestations.