MCLKMemory Clock
MCLKMaster Clock
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As can be seen from the table, tint value is independent of the OAM configuration because it only depends on the frequency of the CPU clock (MCLK).
The 32-b phase accumulator is clocked by a master clock (MCLK) and on each clock adds either the value of FREQ0 or FREQ1 to the current accumulator total.
The MCU chosen is MSP430F2618, which is a 16-bit ultra-low-power RISC MCU; the MCLK is up to 16 MHz, and the wake-up time from low-power mode to active mode is less than 1us, which is suitable for dealing with frequent audio contents.
(2) The network adopts low time synchronization accuracy and lower node MCLK (main clock) to reduce energy consumption.
The high-speed crystal is shutdown when there is no voice communication, the node MCLK drops to about 2 MHz, and TT increases to 65.5 s (i.e., 3200 T; the worst error at 20 ppm is 2.56 ms).